// 
// Copyright (C) 2007 Klaus Hansen and Rasmus Halland
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
// 
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// 
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//

using System;
using System.Collections.Generic;

namespace CellDotNet.Spe
{
	// THIS CLASS IS GENERATED BY CellDotNet.CodeGenUtils.GenerateSpuInstructionWriterMethods() - DO NO EDIT. 
	partial class SpuInstructionWriter
	{
		/// <summary>
		/// Load Quadword (d-form)
		/// </summary>
		public VirtualRegister WriteLqd(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lqd);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Load Quadword (d-form)
		/// </summary>
		public void WriteLqd(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lqd);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Load Quadword (x-form)
		/// </summary>
		public VirtualRegister WriteLqx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lqx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Load Quadword (x-form)
		/// </summary>
		public void WriteLqx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lqx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Load Quadword (a-form)
		/// </summary>
		public VirtualRegister WriteLqa(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lqa);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Load Quadword (a-form)
		/// </summary>
		public void WriteLqa(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lqa);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Load Quadword Instruction Relative (a-form)
		/// </summary>
		public VirtualRegister WriteLqr(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lqr);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Load Quadword Instruction Relative (a-form)
		/// </summary>
		public void WriteLqr(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lqr);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Store Quadword (d-form)
		/// </summary>
		public void WriteStqd(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.stqd);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Store Quadword (x-form)
		/// </summary>
		public void WriteStqx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.stqx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Store Quadword (a-form)
		/// </summary>
		public void WriteStqa(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.stqa);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Store Quadword Instruction Relative (a-form)
		/// </summary>
		public void WriteStqr(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.stqr);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Generate Controls for Byte Insertion (d-form)
		/// </summary>
		public VirtualRegister WriteCbd(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cbd);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Generate Controls for Byte Insertion (d-form)
		/// </summary>
		public void WriteCbd(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cbd);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Generate Controls for Byte Insertion (x-form)
		/// </summary>
		public VirtualRegister WriteCbx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cbx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Generate Controls for Byte Insertion (x-form)
		/// </summary>
		public void WriteCbx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cbx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Generate Controls for Halfword Insertion (d-form)
		/// </summary>
		public VirtualRegister WriteChd(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.chd);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Generate Controls for Halfword Insertion (d-form)
		/// </summary>
		public void WriteChd(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.chd);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Generate Controls for Halfword Insertion (x-form)
		/// </summary>
		public VirtualRegister WriteChx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.chx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Generate Controls for Halfword Insertion (x-form)
		/// </summary>
		public void WriteChx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.chx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Generate Controls for Word Insertion (d-form)
		/// </summary>
		public VirtualRegister WriteCwd(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cwd);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Generate Controls for Word Insertion (d-form)
		/// </summary>
		public void WriteCwd(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cwd);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Generate Controls for Word Insertion (x-form)
		/// </summary>
		public VirtualRegister WriteCwx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cwx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Generate Controls for Word Insertion (x-form)
		/// </summary>
		public void WriteCwx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cwx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Generate Controls for Doubleword Insertion (d-form)
		/// </summary>
		public VirtualRegister WriteCdd(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cdd);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Generate Controls for Doubleword Insertion (d-form)
		/// </summary>
		public void WriteCdd(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cdd);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Generate Controls for Doubleword Insertion (x-form)
		/// </summary>
		public VirtualRegister WriteCdx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cdx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Generate Controls for Doubleword Insertion (x-form)
		/// </summary>
		public void WriteCdx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cdx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Immediate Load Halfword
		/// </summary>
		public VirtualRegister WriteIlh(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ilh);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Immediate Load Halfword
		/// </summary>
		public void WriteIlh(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ilh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Immediate Load Halfword Upper
		/// </summary>
		public VirtualRegister WriteIlhu(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ilhu);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Immediate Load Halfword Upper
		/// </summary>
		public void WriteIlhu(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ilhu);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Immediate Load Word
		/// </summary>
		public VirtualRegister WriteIl(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.il);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Immediate Load Word
		/// </summary>
		public void WriteIl(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.il);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Immediate Load Address
		/// </summary>
		public VirtualRegister WriteIla(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ila);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Immediate Load Address
		/// </summary>
		public void WriteIla(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ila);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Immediate Or Halfword Lower
		/// </summary>
		public VirtualRegister WriteIohl(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.iohl);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Immediate Or Halfword Lower
		/// </summary>
		public void WriteIohl(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.iohl);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Form Select Mask for Bytes Immediate
		/// </summary>
		public VirtualRegister WriteFsmbi(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fsmbi);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Form Select Mask for Bytes Immediate
		/// </summary>
		public void WriteFsmbi(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fsmbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Add Halfword
		/// </summary>
		public VirtualRegister WriteAh(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ah);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Add Halfword
		/// </summary>
		public void WriteAh(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ah);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Add Halfword Immediate
		/// </summary>
		public VirtualRegister WriteAhi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ahi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Add Halfword Immediate
		/// </summary>
		public void WriteAhi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ahi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Add Word
		/// </summary>
		public VirtualRegister WriteA(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.a);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Add Word
		/// </summary>
		public void WriteA(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.a);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Add Word Immediate
		/// </summary>
		public VirtualRegister WriteAi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ai);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Add Word Immediate
		/// </summary>
		public void WriteAi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ai);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Subtract from Halfword
		/// </summary>
		public VirtualRegister WriteSfh(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sfh);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Subtract from Halfword
		/// </summary>
		public void WriteSfh(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sfh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Subtract from Halfword Immediate
		/// </summary>
		public VirtualRegister WriteSfhi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sfhi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Subtract from Halfword Immediate
		/// </summary>
		public void WriteSfhi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sfhi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Subtract from Word
		/// </summary>
		public VirtualRegister WriteSf(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sf);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Subtract from Word
		/// </summary>
		public void WriteSf(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sf);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Subtract from Word Immediate
		/// </summary>
		public VirtualRegister WriteSfi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sfi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Subtract from Word Immediate
		/// </summary>
		public void WriteSfi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sfi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Add Extended
		/// </summary>
		public VirtualRegister WriteAddx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.addx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Add Extended
		/// </summary>
		public void WriteAddx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.addx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Carry Generate
		/// </summary>
		public VirtualRegister WriteCg(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cg);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Carry Generate
		/// </summary>
		public void WriteCg(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cg);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Carry Generate Extended
		/// </summary>
		public VirtualRegister WriteCgx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Carry Generate Extended
		/// </summary>
		public void WriteCgx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Subtract from Extended
		/// </summary>
		public VirtualRegister WriteSfx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sfx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Subtract from Extended
		/// </summary>
		public void WriteSfx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sfx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Borrow Generate
		/// </summary>
		public VirtualRegister WriteBg(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bg);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Borrow Generate
		/// </summary>
		public void WriteBg(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bg);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Borrow Generate Extended
		/// </summary>
		public VirtualRegister WriteBgx(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bgx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Borrow Generate Extended
		/// </summary>
		public void WriteBgx(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bgx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply
		/// </summary>
		public VirtualRegister WriteMpy(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpy);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply
		/// </summary>
		public void WriteMpy(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpy);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply Unsigned
		/// </summary>
		public VirtualRegister WriteMpyu(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyu);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply Unsigned
		/// </summary>
		public void WriteMpyu(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyu);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply Immediate
		/// </summary>
		public VirtualRegister WriteMpyi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply Immediate
		/// </summary>
		public void WriteMpyi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply Unsigned Immediate
		/// </summary>
		public VirtualRegister WriteMpyui(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyui);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply Unsigned Immediate
		/// </summary>
		public void WriteMpyui(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyui);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply and Add
		/// </summary>
		public VirtualRegister WriteMpya(VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpya);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply and Add
		/// </summary>
		public void WriteMpya(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpya);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply High
		/// </summary>
		public VirtualRegister WriteMpyh(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyh);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply High
		/// </summary>
		public void WriteMpyh(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply and Shift Right
		/// </summary>
		public VirtualRegister WriteMpys(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpys);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply and Shift Right
		/// </summary>
		public void WriteMpys(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpys);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply High High
		/// </summary>
		public VirtualRegister WriteMpyhh(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyhh);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply High High
		/// </summary>
		public void WriteMpyhh(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyhh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply High High and Add
		/// </summary>
		public VirtualRegister WriteMpyhha(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyhha);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply High High and Add
		/// </summary>
		public void WriteMpyhha(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyhha);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply High High Unsigned
		/// </summary>
		public VirtualRegister WriteMpyhhu(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyhhu);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply High High Unsigned
		/// </summary>
		public void WriteMpyhhu(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyhhu);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Multiply High High Unsigned and Add
		/// </summary>
		public VirtualRegister WriteMpyhhau(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyhhau);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Multiply High High Unsigned and Add
		/// </summary>
		public void WriteMpyhhau(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.mpyhhau);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Count Leading Zeros
		/// </summary>
		public VirtualRegister WriteClz(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clz);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Count Leading Zeros
		/// </summary>
		public void WriteClz(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Count Ones in Bytes
		/// </summary>
		public VirtualRegister WriteCntb(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cntb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Count Ones in Bytes
		/// </summary>
		public void WriteCntb(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cntb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Form Select Mask for Bytes
		/// </summary>
		public VirtualRegister WriteFsmb(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fsmb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Form Select Mask for Bytes
		/// </summary>
		public void WriteFsmb(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fsmb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Form Select Mask for Halfwords
		/// </summary>
		public VirtualRegister WriteFsmh(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fsmh);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Form Select Mask for Halfwords
		/// </summary>
		public void WriteFsmh(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fsmh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Form Select Mask for Words
		/// </summary>
		public VirtualRegister WriteFsm(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fsm);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Form Select Mask for Words
		/// </summary>
		public void WriteFsm(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fsm);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Gather Bits from Bytes
		/// </summary>
		public VirtualRegister WriteGbb(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.gbb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Gather Bits from Bytes
		/// </summary>
		public void WriteGbb(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.gbb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Gather Bits from Halfwords
		/// </summary>
		public VirtualRegister WriteGbh(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.gbh);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Gather Bits from Halfwords
		/// </summary>
		public void WriteGbh(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.gbh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Gather Bits from Words
		/// </summary>
		public VirtualRegister WriteGb(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.gb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Gather Bits from Words
		/// </summary>
		public void WriteGb(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.gb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Average Bytes
		/// </summary>
		public VirtualRegister WriteAvgb(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.avgb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Average Bytes
		/// </summary>
		public void WriteAvgb(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.avgb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Absolute Differences of Bytes
		/// </summary>
		public VirtualRegister WriteAbsdb(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.absdb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Absolute Differences of Bytes
		/// </summary>
		public void WriteAbsdb(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.absdb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Sum Bytes into Halfwords
		/// </summary>
		public VirtualRegister WriteSumb(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sumb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Sum Bytes into Halfwords
		/// </summary>
		public void WriteSumb(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.sumb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Extend Sign Byte to Halfword
		/// </summary>
		public VirtualRegister WriteXsbh(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xsbh);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Extend Sign Byte to Halfword
		/// </summary>
		public void WriteXsbh(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xsbh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Extend Sign Halfword to Word
		/// </summary>
		public VirtualRegister WriteXshw(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xshw);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Extend Sign Halfword to Word
		/// </summary>
		public void WriteXshw(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xshw);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Extend Sign Word to Doubleword
		/// </summary>
		public VirtualRegister WriteXswd(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xswd);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Extend Sign Word to Doubleword
		/// </summary>
		public void WriteXswd(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xswd);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// And
		/// </summary>
		public VirtualRegister WriteAnd(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.and);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// And
		/// </summary>
		public void WriteAnd(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.and);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// And with Complement
		/// </summary>
		public VirtualRegister WriteAndc(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.andc);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// And with Complement
		/// </summary>
		public void WriteAndc(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.andc);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// And Byte Immediate
		/// </summary>
		public VirtualRegister WriteAndbi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.andbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// And Byte Immediate
		/// </summary>
		public void WriteAndbi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.andbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// And Halfword Immediate
		/// </summary>
		public VirtualRegister WriteAndhi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.andhi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// And Halfword Immediate
		/// </summary>
		public void WriteAndhi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.andhi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// And Word Immediate
		/// </summary>
		public VirtualRegister WriteAndi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.andi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// And Word Immediate
		/// </summary>
		public void WriteAndi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.andi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Or
		/// </summary>
		public VirtualRegister WriteOr(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.or);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Or
		/// </summary>
		public void WriteOr(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.or);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Or with Complement
		/// </summary>
		public VirtualRegister WriteOrc(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.orc);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Or with Complement
		/// </summary>
		public void WriteOrc(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.orc);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Or Byte Immediate
		/// </summary>
		public VirtualRegister WriteOrbi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.orbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Or Byte Immediate
		/// </summary>
		public void WriteOrbi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.orbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Or Halfword Immediate
		/// </summary>
		public VirtualRegister WriteOrhi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.orhi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Or Halfword Immediate
		/// </summary>
		public void WriteOrhi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.orhi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Or Word Immediate
		/// </summary>
		public VirtualRegister WriteOri(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ori);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Or Word Immediate
		/// </summary>
		public void WriteOri(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ori);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Or Across
		/// </summary>
		public VirtualRegister WriteOrx(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.orx);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Or Across
		/// </summary>
		public void WriteOrx(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.orx);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Exclusive Or
		/// </summary>
		public VirtualRegister WriteXor(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xor);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Exclusive Or
		/// </summary>
		public void WriteXor(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xor);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Exclusive Or Byte Immediate
		/// </summary>
		public VirtualRegister WriteXorbi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xorbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Exclusive Or Byte Immediate
		/// </summary>
		public void WriteXorbi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xorbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Exclusive Or Halfword Immediate
		/// </summary>
		public VirtualRegister WriteXorhi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xorhi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Exclusive Or Halfword Immediate
		/// </summary>
		public void WriteXorhi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xorhi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Exclusive Or Word Immediate
		/// </summary>
		public VirtualRegister WriteXori(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xori);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Exclusive Or Word Immediate
		/// </summary>
		public void WriteXori(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.xori);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Nand
		/// </summary>
		public VirtualRegister WriteNand(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.nand);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Nand
		/// </summary>
		public void WriteNand(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.nand);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Nor
		/// </summary>
		public VirtualRegister WriteNor(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.nor);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Nor
		/// </summary>
		public void WriteNor(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.nor);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Equivalent
		/// </summary>
		public VirtualRegister WriteEqv(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.eqv);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Equivalent
		/// </summary>
		public void WriteEqv(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.eqv);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Select Bits
		/// </summary>
		public VirtualRegister WriteSelb(VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.selb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Select Bits
		/// </summary>
		public void WriteSelb(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.selb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);

		}

		/// <summary>
		/// Shuffle Bytes
		/// </summary>
		public VirtualRegister WriteShufb(VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shufb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shuffle Bytes
		/// </summary>
		public void WriteShufb(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shufb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Halfword
		/// </summary>
		public VirtualRegister WriteShlh(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlh);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Halfword
		/// </summary>
		public void WriteShlh(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Halfword Immediate
		/// </summary>
		public VirtualRegister WriteShlhi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlhi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Halfword Immediate
		/// </summary>
		public void WriteShlhi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlhi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Word
		/// </summary>
		public VirtualRegister WriteShl(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shl);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Word
		/// </summary>
		public void WriteShl(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shl);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Word Immediate
		/// </summary>
		public VirtualRegister WriteShli(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shli);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Word Immediate
		/// </summary>
		public void WriteShli(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shli);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Quadword by Bits
		/// </summary>
		public VirtualRegister WriteShlqbi(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Quadword by Bits
		/// </summary>
		public void WriteShlqbi(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Quadword by Bits Immediate
		/// </summary>
		public VirtualRegister WriteShlqbii(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqbii);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Quadword by Bits Immediate
		/// </summary>
		public void WriteShlqbii(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqbii);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Quadword by Bytes
		/// </summary>
		public VirtualRegister WriteShlqby(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqby);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Quadword by Bytes
		/// </summary>
		public void WriteShlqby(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqby);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Quadword by Bytes Immediate
		/// </summary>
		public VirtualRegister WriteShlqbyi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqbyi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Quadword by Bytes Immediate
		/// </summary>
		public void WriteShlqbyi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqbyi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Shift Left Quadword by Bytes from Bit Shift Count
		/// </summary>
		public VirtualRegister WriteShlqbybi(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqbybi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Shift Left Quadword by Bytes from Bit Shift Count
		/// </summary>
		public void WriteShlqbybi(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.shlqbybi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Halfword
		/// </summary>
		public VirtualRegister WriteRoth(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.roth);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Halfword
		/// </summary>
		public void WriteRoth(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.roth);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Halfword Immediate
		/// </summary>
		public VirtualRegister WriteRothi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rothi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Halfword Immediate
		/// </summary>
		public void WriteRothi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rothi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Word
		/// </summary>
		public VirtualRegister WriteRot(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rot);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Word
		/// </summary>
		public void WriteRot(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rot);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Word Immediate
		/// </summary>
		public VirtualRegister WriteRoti(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.roti);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Word Immediate
		/// </summary>
		public void WriteRoti(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.roti);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Quadword by Bytes
		/// </summary>
		public VirtualRegister WriteRotqby(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqby);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Quadword by Bytes
		/// </summary>
		public void WriteRotqby(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqby);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Quadword by Bytes Immediate
		/// </summary>
		public VirtualRegister WriteRotqbyi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqbyi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Quadword by Bytes Immediate
		/// </summary>
		public void WriteRotqbyi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqbyi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Quadword by Bytes from Bit Shift Count
		/// </summary>
		public VirtualRegister WriteRotqbybi(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqbybi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Quadword by Bytes from Bit Shift Count
		/// </summary>
		public void WriteRotqbybi(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqbybi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Quadword by Bits
		/// </summary>
		public VirtualRegister WriteRotqbi(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Quadword by Bits
		/// </summary>
		public void WriteRotqbi(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate Quadword by Bits Immediate
		/// </summary>
		public VirtualRegister WriteRotqbii(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqbii);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate Quadword by Bits Immediate
		/// </summary>
		public void WriteRotqbii(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqbii);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Halfword
		/// </summary>
		public VirtualRegister WriteRothm(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rothm);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Halfword
		/// </summary>
		public void WriteRothm(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rothm);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Halfword Immediate
		/// </summary>
		public VirtualRegister WriteRothmi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rothmi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Halfword Immediate
		/// </summary>
		public void WriteRothmi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rothmi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Word
		/// </summary>
		public VirtualRegister WriteRotm(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotm);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Word
		/// </summary>
		public void WriteRotm(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotm);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Word Immediate
		/// </summary>
		public VirtualRegister WriteRotmi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotmi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Word Immediate
		/// </summary>
		public void WriteRotmi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotmi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Quadword by Bytes
		/// </summary>
		public VirtualRegister WriteRotqmby(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmby);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Quadword by Bytes
		/// </summary>
		public void WriteRotqmby(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmby);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Quadword by Bytes Immediate
		/// </summary>
		public VirtualRegister WriteRotqmbyi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmbyi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Quadword by Bytes Immediate
		/// </summary>
		public void WriteRotqmbyi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmbyi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Quadword Bytes from Bit Shift Count
		/// </summary>
		public VirtualRegister WriteRotqmbybi(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmbybi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Quadword Bytes from Bit Shift Count
		/// </summary>
		public void WriteRotqmbybi(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmbybi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Quadword by Bits
		/// </summary>
		public VirtualRegister WriteRotqmbi(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Quadword by Bits
		/// </summary>
		public void WriteRotqmbi(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Quadword by Bits Immediate
		/// </summary>
		public VirtualRegister WriteRotqmbii(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmbii);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Quadword by Bits Immediate
		/// </summary>
		public void WriteRotqmbii(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotqmbii);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Algebraic Halfword
		/// </summary>
		public VirtualRegister WriteRotmah(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotmah);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Algebraic Halfword
		/// </summary>
		public void WriteRotmah(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotmah);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Algebraic Halfword Immediate
		/// </summary>
		public VirtualRegister WriteRotmahi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotmahi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Algebraic Halfword Immediate
		/// </summary>
		public void WriteRotmahi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotmahi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Algebraic Word
		/// </summary>
		public VirtualRegister WriteRotma(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotma);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Algebraic Word
		/// </summary>
		public void WriteRotma(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotma);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Rotate and Mask Algebraic Word Immediate
		/// </summary>
		public VirtualRegister WriteRotmai(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotmai);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Rotate and Mask Algebraic Word Immediate
		/// </summary>
		public void WriteRotmai(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rotmai);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Halt If Equal
		/// </summary>
		public VirtualRegister WriteHeq(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.heq);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Halt If Equal
		/// </summary>
		public void WriteHeq(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.heq);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Halt If Equal Immediate
		/// </summary>
		public VirtualRegister WriteHeqi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.heqi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Halt If Equal Immediate
		/// </summary>
		public void WriteHeqi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.heqi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Halt If Greater Than
		/// </summary>
		public VirtualRegister WriteHgt(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.hgt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Halt If Greater Than
		/// </summary>
		public void WriteHgt(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.hgt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Halt If Greater Than Immediate
		/// </summary>
		public VirtualRegister WriteHgti(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.hgti);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Halt If Greater Than Immediate
		/// </summary>
		public void WriteHgti(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.hgti);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Halt If Logically Greater Than
		/// </summary>
		public VirtualRegister WriteHlgt(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.hlgt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Halt If Logically Greater Than
		/// </summary>
		public void WriteHlgt(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.hlgt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Halt If Logically Greater Than Immediate
		/// </summary>
		public VirtualRegister WriteHlgti(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.hlgti);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Halt If Logically Greater Than Immediate
		/// </summary>
		public void WriteHlgti(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.hlgti);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Equal Byte
		/// </summary>
		public VirtualRegister WriteCeqb(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Equal Byte
		/// </summary>
		public void WriteCeqb(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Equal Byte Immediate
		/// </summary>
		public VirtualRegister WriteCeqbi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Equal Byte Immediate
		/// </summary>
		public void WriteCeqbi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Equal Halfword
		/// </summary>
		public VirtualRegister WriteCeqh(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqh);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Equal Halfword
		/// </summary>
		public void WriteCeqh(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqh);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Equal Halfword Immediate
		/// </summary>
		public VirtualRegister WriteCeqhi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqhi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Equal Halfword Immediate
		/// </summary>
		public void WriteCeqhi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqhi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Equal Word
		/// </summary>
		public VirtualRegister WriteCeq(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceq);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Equal Word
		/// </summary>
		public void WriteCeq(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceq);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Equal Word Immediate
		/// </summary>
		public VirtualRegister WriteCeqi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Equal Word Immediate
		/// </summary>
		public void WriteCeqi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.ceqi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Greater Than Byte
		/// </summary>
		public VirtualRegister WriteCgtb(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgtb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Greater Than Byte
		/// </summary>
		public void WriteCgtb(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgtb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Greater Than Byte Immediate
		/// </summary>
		public VirtualRegister WriteCgtbi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgtbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Greater Than Byte Immediate
		/// </summary>
		public void WriteCgtbi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgtbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Greater Than Halfword
		/// </summary>
		public VirtualRegister WriteCgth(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgth);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Greater Than Halfword
		/// </summary>
		public void WriteCgth(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgth);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Greater Than Halfword Immediate
		/// </summary>
		public VirtualRegister WriteCgthi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgthi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Greater Than Halfword Immediate
		/// </summary>
		public void WriteCgthi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgthi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Greater Than Word
		/// </summary>
		public VirtualRegister WriteCgt(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Greater Than Word
		/// </summary>
		public void WriteCgt(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Greater Than Word Immediate
		/// </summary>
		public VirtualRegister WriteCgti(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgti);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Greater Than Word Immediate
		/// </summary>
		public void WriteCgti(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cgti);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Logical Greater Than Byte
		/// </summary>
		public VirtualRegister WriteClgtb(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgtb);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Logical Greater Than Byte
		/// </summary>
		public void WriteClgtb(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgtb);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Logical Greater Than Byte Immediate
		/// </summary>
		public VirtualRegister WriteClgtbi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgtbi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Logical Greater Than Byte Immediate
		/// </summary>
		public void WriteClgtbi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgtbi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Logical Greater Than Halfword
		/// </summary>
		public VirtualRegister WriteClgth(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgth);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Logical Greater Than Halfword
		/// </summary>
		public void WriteClgth(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgth);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Logical Greater Than Halfword Immediate
		/// </summary>
		public VirtualRegister WriteClgthi(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgthi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Logical Greater Than Halfword Immediate
		/// </summary>
		public void WriteClgthi(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgthi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Logical Greater Than Word
		/// </summary>
		public VirtualRegister WriteClgt(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Logical Greater Than Word
		/// </summary>
		public void WriteClgt(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Compare Logical Greater Than Word Immediate
		/// </summary>
		public VirtualRegister WriteClgti(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgti);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Compare Logical Greater Than Word Immediate
		/// </summary>
		public void WriteClgti(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.clgti);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch Relative
		/// </summary>
		public VirtualRegister WriteBr(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.br);
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Branch Absolute
		/// </summary>
		public VirtualRegister WriteBra(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bra);
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Branch Relative and Set Link
		/// </summary>
		public VirtualRegister WriteBrsl(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.brsl);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Branch Relative and Set Link
		/// </summary>
		public void WriteBrsl(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.brsl);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch Absolute and Set Link
		/// </summary>
		public VirtualRegister WriteBrasl(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.brasl);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Branch Absolute and Set Link
		/// </summary>
		public void WriteBrasl(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.brasl);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch Indirect
		/// </summary>
		public VirtualRegister WriteBi(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bi);
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Interrupt Return
		/// </summary>
		public VirtualRegister WriteIret(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.iret);
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Branch Indirect and Set Link if External Data
		/// </summary>
		public VirtualRegister WriteBisled(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bisled);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Branch Indirect and Set Link if External Data
		/// </summary>
		public void WriteBisled(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bisled);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch Indirect and Set Link
		/// </summary>
		public VirtualRegister WriteBisl(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bisl);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Branch Indirect and Set Link
		/// </summary>
		public void WriteBisl(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bisl);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch If Not Zero Word
		/// </summary>
		public void WriteBrnz(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.brnz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch If Zero Word
		/// </summary>
		public void WriteBrz(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.brz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch If Not Zero Halfword
		/// </summary>
		public void WriteBrhnz(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.brhnz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch If Zero Halfword
		/// </summary>
		public void WriteBrhz(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.brhz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch Indirect If Zero
		/// </summary>
		public void WriteBiz(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.biz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch Indirect If Not Zero
		/// </summary>
		public void WriteBinz(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.binz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch Indirect If Zero Halfword
		/// </summary>
		public void WriteBihz(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bihz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Branch Indirect If Not Zero Halfword
		/// </summary>
		public void WriteBihnz(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.bihnz);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Add
		/// </summary>
		public VirtualRegister WriteFa(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fa);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Add
		/// </summary>
		public void WriteFa(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fa);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Add
		/// </summary>
		public VirtualRegister WriteDfa(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfa);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Add
		/// </summary>
		public void WriteDfa(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfa);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Subtract
		/// </summary>
		public VirtualRegister WriteFs(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fs);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Subtract
		/// </summary>
		public void WriteFs(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fs);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Subtract
		/// </summary>
		public VirtualRegister WriteDfs(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfs);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Subtract
		/// </summary>
		public void WriteDfs(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfs);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Multiply
		/// </summary>
		public VirtualRegister WriteFm(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fm);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Multiply
		/// </summary>
		public void WriteFm(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fm);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Multiply
		/// </summary>
		public VirtualRegister WriteDfm(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfm);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Multiply
		/// </summary>
		public void WriteDfm(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfm);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Multiply and Add
		/// </summary>
		public VirtualRegister WriteFma(VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fma);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Multiply and Add
		/// </summary>
		public void WriteFma(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fma);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Multiply and Add
		/// </summary>
		public VirtualRegister WriteDfma(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfma);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Multiply and Add
		/// </summary>
		public void WriteDfma(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfma);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Negative Multiply and Subtract
		/// </summary>
		public VirtualRegister WriteFnms(VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fnms);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Negative Multiply and Subtract
		/// </summary>
		public void WriteFnms(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fnms);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Negative Multiply and Subtract
		/// </summary>
		public VirtualRegister WriteDfnms(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfnms);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Negative Multiply and Subtract
		/// </summary>
		public void WriteDfnms(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfnms);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Multiply and Subtract
		/// </summary>
		public VirtualRegister WriteFms(VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fms);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Multiply and Subtract
		/// </summary>
		public void WriteFms(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb, VirtualRegister rc)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fms);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			inst.Rc = rc;
			AssertRegisterNotNull(rc, "rc");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Multiply and Subtract
		/// </summary>
		public VirtualRegister WriteDfms(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfms);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Multiply and Subtract
		/// </summary>
		public void WriteDfms(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfms);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Negative Multiply and Add
		/// </summary>
		public VirtualRegister WriteDfnma(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfnma);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Negative Multiply and Add
		/// </summary>
		public void WriteDfnma(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfnma);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Reciprocal Estimate
		/// </summary>
		public VirtualRegister WriteFrest(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.frest);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Reciprocal Estimate
		/// </summary>
		public void WriteFrest(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.frest);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Reciprocal Absolute Square Root Estimate
		/// </summary>
		public VirtualRegister WriteFrsqest(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.frsqest);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Reciprocal Absolute Square Root Estimate
		/// </summary>
		public void WriteFrsqest(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.frsqest);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Interpolate
		/// </summary>
		public VirtualRegister WriteFi(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fi);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Interpolate
		/// </summary>
		public void WriteFi(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fi);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Convert Signed Integer to Floating
		/// </summary>
		public VirtualRegister WriteCsflt(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.csflt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Convert Signed Integer to Floating
		/// </summary>
		public void WriteCsflt(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.csflt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Convert Floating to Signed Integer
		/// </summary>
		public VirtualRegister WriteCflts(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cflts);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Convert Floating to Signed Integer
		/// </summary>
		public void WriteCflts(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cflts);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Convert Unsigned Integer to Floating
		/// </summary>
		public VirtualRegister WriteCuflt(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cuflt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Convert Unsigned Integer to Floating
		/// </summary>
		public void WriteCuflt(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cuflt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Convert Floating to Unsigned Integer
		/// </summary>
		public VirtualRegister WriteCfltu(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cfltu);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Convert Floating to Unsigned Integer
		/// </summary>
		public void WriteCfltu(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.cfltu);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Round Double to Single
		/// </summary>
		public VirtualRegister WriteFrds(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.frds);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Round Double to Single
		/// </summary>
		public void WriteFrds(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.frds);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Extend Single to Double
		/// </summary>
		public VirtualRegister WriteFesd(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fesd);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Extend Single to Double
		/// </summary>
		public void WriteFesd(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fesd);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Compare Equal
		/// </summary>
		public VirtualRegister WriteDfceq(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfceq);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Compare Equal
		/// </summary>
		public void WriteDfceq(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfceq);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Compare Magnitude Equal
		/// </summary>
		public VirtualRegister WriteDfcmeq(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfcmeq);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Compare Magnitude Equal
		/// </summary>
		public void WriteDfcmeq(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfcmeq);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Compare Greater Than
		/// </summary>
		public VirtualRegister WriteDfcgt(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfcgt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Compare Greater Than
		/// </summary>
		public void WriteDfcgt(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfcgt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Compare Magnitude Greater Than
		/// </summary>
		public VirtualRegister WriteDfcmgt(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfcmgt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Compare Magnitude Greater Than
		/// </summary>
		public void WriteDfcmgt(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dfcmgt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Double Floating Test Special Value
		/// </summary>
		public VirtualRegister WriteDftsv(VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dftsv);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Double Floating Test Special Value
		/// </summary>
		public void WriteDftsv(VirtualRegister rt, VirtualRegister ra, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.dftsv);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Compare Equal
		/// </summary>
		public VirtualRegister WriteFceq(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fceq);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Compare Equal
		/// </summary>
		public void WriteFceq(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fceq);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Compare Magnitude Equal
		/// </summary>
		public VirtualRegister WriteFcmeq(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fcmeq);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Compare Magnitude Equal
		/// </summary>
		public void WriteFcmeq(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fcmeq);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Compare Greater Than
		/// </summary>
		public VirtualRegister WriteFcgt(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fcgt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Compare Greater Than
		/// </summary>
		public void WriteFcgt(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fcgt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating Compare Magnitude Greater Than
		/// </summary>
		public VirtualRegister WriteFcmgt(VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fcmgt);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating Compare Magnitude Greater Than
		/// </summary>
		public void WriteFcmgt(VirtualRegister rt, VirtualRegister ra, VirtualRegister rb)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fcmgt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			inst.Rb = rb;
			AssertRegisterNotNull(rb, "rb");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating-Point Status and Control Register Write
		/// </summary>
		public VirtualRegister WriteFscrwr(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fscrwr);
			inst.Rt = NextRegister();
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Floating-Point Status and Control Register Write
		/// </summary>
		public void WriteFscrwr(VirtualRegister rt, VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fscrwr);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);

		}

		/// <summary>
		/// Floating-Point Status and Control Register Read
		/// </summary>
		public VirtualRegister WriteFscrrd(VirtualRegister ra)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.fscrrd);
			inst.Ra = ra;
			AssertRegisterNotNull(ra, "ra");
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Stop and Signal
		/// </summary>
		public void WriteStop()
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.stop);
			AddInstruction(inst);

		}

		/// <summary>
		/// No Operation (Load)
		/// </summary>
		public void WriteLnop()
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.lnop);
			AddInstruction(inst);

		}

		/// <summary>
		/// No Operation (Execute)
		/// </summary>
		public void WriteNop()
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.nop);
			AddInstruction(inst);

		}

		/// <summary>
		/// Read Channel
		/// </summary>
		public VirtualRegister WriteRdch(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rdch);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Read Channel
		/// </summary>
		public void WriteRdch(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rdch);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Read Channel Count
		/// </summary>
		public VirtualRegister WriteRchcnt(int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rchcnt);
			inst.Rt = NextRegister();
			inst.Constant = immediate;
			AddInstruction(inst);
			return inst.Rt;

		}

		/// <summary>
		/// Read Channel Count
		/// </summary>
		public void WriteRchcnt(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.rchcnt);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}

		/// <summary>
		/// Write Channel
		/// </summary>
		public void WriteWrch(VirtualRegister rt, int immediate)
		{
			SpuInstruction inst = new SpuInstruction(SpuOpCode.wrch);
			AssertRegisterNotNull(rt, "rt");
			inst.Rt = rt;
			inst.Constant = immediate;
			AddInstruction(inst);

		}
	}
}
